SynSense dedicated to developing core chips for next-generation human-machine and brain-computers. Its technology is built around the principles of sensing-computing integration and ultra-low power consumption, enabling highly efficient and responsive intelligent systems .

Founded by Dr. Ning Qiao of the Chinese Academy of Sciences and Professor Giacomo Indiveri of The Institute of Neuroinformatics (INI), the company leverages over two decades of pioneering research from the University of Zurich and ETH Zurich. With R&D personnel accounting for 75% of its workforce, SynSense has established in Shanghai, Ningbo, Chengdu, and Zurich, forming a full-stack technological capability.
SynSense has earned prestigious accolades including the CES Innovation Award and the Ministry of Science and Technology’s Disruptive Innovation Award. Looking ahead, the company plans to expand into the upstream brain-computer ecosystem by integrating “electrode + chip” modules, contributing China’s vision and solutions to the global AI industry.
iniVation , a SynSense Group company , is a global leader in high-performance vision systems. Its complete portfolio of frame-based and bio-inspired technology delivers breakthrough advantages across multiple applications, including ultra-low latency, extreme dynamic range, and ultra-low power consumption.

Job Profile:

To drive the development of our next-generation visual sensors, we are seeking a core member to lead the high-performance advancement of state-of-the-art CMOS Image Sensors (CIS). This position will take full ownership of the analog front-end (AFE) circuit design—the key to achieving high image quality and wide dynamic range—along with high-level layout guidance, and the bench evaluation and debugging of test chips and mass-production silicon. We are looking for an expert who can lead the entire process, from architectural conception to hands-on performance validation and successful mass production.

Job Details:

Responsibilities:

Take full responsibility for the analog front-end circuit design of CMOS image sensors, as well as the evaluation and debugging of actual silicon.

Analog Circuit Design & Layout Guidance
・Lead the architecture and transistor-level design of high-performance column-parallel ADCs (Single-slope, SAR, Cyclic, etc.) for CIS.
・Design HDR pixel readout circuits utilizing advanced technologies such as DCG (Dual Conversion Gain), LOFIC (Lateral Overflow Integration Capacitor), and DAG (Dual Analog Gain).
・Provide detailed design guidance to layout engineers (including floorplanning, routing with crosstalk and noise countermeasures, and device matching).
・Perform performance verification and optimization through parasitic extraction and post-layout simulation.

Silicon Evaluation & Debugging
・Develop and execute evaluation plans for test chips and mass-production silicon.
・Conduct hands-on bench evaluation and characterization (noise analysis, linearity evaluation, etc.) in the lab, performing root-cause analysis and debugging when anomalies arise.

Mass Production Support
・Collaborate closely with pixel design, digital design, testing engineers, and foundries to provide technical leadership from tape-out to mass production yield improvement.

Qualifications:

Requirements
・Solid hands-on experience in analog IC design, as well as silicon evaluation and debugging (reference: 5+ years).
・Extensive experience in the design and evaluation of ADC modules.
・Knowledge and design experience in image sensor circuits utilizing at least one (or more) of the following technologies: DCG, LOFIC, or DAG.
・Proven ability to accurately convey circuit design intent to layout engineers and successfully achieve high-precision layouts.
・Mass production experience with CMOS Image Sensors (a track record of bringing self-designed and evaluated products to market).
・Proficiency with lab testing instruments (oscilloscopes, spectrum analyzers, logic analyzers, multimeters, etc.) and advanced troubleshooting skills.
・Proficiency in using EDA tools such as Cadence Virtuoso for design and verification.

Preferred Qualifications
・Knowledge and design/evaluation experience related to Global Shutter architectures.
・Experience in design and mass production utilizing cutting-edge processes, such as stacked CIS (e.g., Cu-Cu hybrid bonding) and 3D-MIM capacitors.
・Technical communication skills in English.

Benefit:

Transportation allowance
meal allowance
Quarterly performance bonus
annual performance bonus

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