SynSense dedicated to developing core chips for next-generation human-machine and brain-computers. Its technology is built around the principles of sensing-computing integration and ultra-low power consumption, enabling highly efficient and responsive intelligent systems .
Founded by Dr. Ning Qiao of the Chinese Academy of Sciences and Professor Giacomo Indiveri of The Institute of Neuroinformatics (INI), the company leverages over two decades of pioneering research from the University of Zurich and ETH Zurich. With R&D personnel accounting for 75% of its workforce, SynSense has established in Shanghai, Ningbo, Chengdu, and Zurich, forming a full-stack technological capability.
SynSense has earned prestigious accolades including the CES Innovation Award and the Ministry of Science and Technology’s Disruptive Innovation Award. Looking ahead, the company plans to expand into the upstream brain-computer ecosystem by integrating “electrode + chip” modules, contributing China’s vision and solutions to the global AI industry.
iniVation , a SynSense Group company , is a global leader in high-performance vision systems. Its complete portfolio of frame-based and bio-inspired technology delivers breakthrough advantages across multiple applications, including ultra-low latency, extreme dynamic range, and ultra-low power consumption.

Job Profile:

A former Huawei Level 21 expert is currently building a team.

Job Details:

Responsibilities:

(1) **TCAD Simulation & Calibration:** Perform comprehensive device and process simulations using TCAD to evaluate and optimize pixel performance. Rigorously calibrate TCAD models against measured silicon data to ensure predictive accuracy and manufacturing robustness;
(2) **Layout & Test Structure Design:** Use EDA tools such as Cadence Virtuoso for pixel layout and test structure (Test Key) design and routing, and strictly execute physical verification flows including DRC and LVS;
(3) **Foundry Collaboration:** Partner with external foundries to optimize process conditions and define DOE splits for experimental lots;
(4) **Data Analysis & Evaluation:** Work with test engineers to analyze measurement data from prototype wafers and evaluate pixel characteristics (e.g., extract SNR, sensitivity, dark current, and other parameters); collaborate with analog circuit design teams and system engineers on co-design and troubleshooting.

Qualifications:

(1) Deep understanding of semiconductor physics, device physics, and CMOS optoelectronics technology;
(2) Hands-on experience in image sensor pixel design or related semiconductor process development, with a strong focus on device modeling;
(3) Proficiency in TCAD (2D/3D) simulation, as well as industry-standard layout design and physical verification EDA tools;
(4) Excellent communication and interpersonal skills, with the ability to collaborate effectively with cross-functional teams (analog/logic design, test & characterization, process engineering, etc.) to resolve complex technical challenges.

**Preferred Qualifications (Plus):**
(1) Familiarity with advanced pixel architectures, particularly Global Shutter design;
(2) Experience with optical simulation (e.g., FDTD), including Chief Ray Angle (CRA) analysis and microlens shift optimization;
(3) Proven track record of designing high-resolution sensors (e.g., 3MP to 5MP) with small pixel sizes (e.g., 2.2µm or smaller);
(4) Ability to communicate effectively in English or Chinese with international partners and foundries for technical discussions and business coordination.

Benefit:

2 months' salary. In addition, meal allowance and transportation allowance are provided.

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